Microsoft Download Center Archive
 | Speedy DDR2 Controller for FPGAs |
The Speedy DDR2 controller is intended as an improvement on the Xilinx MIG controller for Virtex 5 FPGAs. Last published: March 18, 2011.
- The Speedy DDR2 controller is intended as an improvement on the Xilinx MIG controller for Virtex 5 FPGAs. Designed entirely from scratch on the ML505 development board, it achieves better performance at the same clock rate than the MIG controller while consuming comparable resources. The tight timing constraints imposed by high-speed DDR2 clash with the worst-case timing constraint style of FPGA design in a way that presents unique challenges. This paper discusses the primary design problems resulting from that paradox and contrasts approaches to their solutions. Performance then is compared between the Speedy DDR2 controller and the Xilinx MIG controller. The source code has been written to be more readable, maintainable, and modifiable than the MIG design and is freely downloadable from the Web.
Files
 | Status: LiveThis download is still available on microsoft.com. The downloads below will come directly from the Microsoft Download Center. |
| File | Size |
|---|---|
 SpeedyDDR2ControllerForFPGAs_1_1.msiSHA1: 9a6e1b5056915cdaaed97b40ab3495e293fd0905 | 313 KB |
File sizes and hashes are retrieved from the Wayback Machine’s indexes. They may not match the latest versions of files hosted on Microsoft servers.
System Requirements
Operating Systems: Windows 10, Windows 7, Windows 8
- Windows 7, Windows 8, or Windows 10
Installation Instructions
- Click Download and follow the instructions.